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mos integrated circuit pd9991 ring tone generator lsi (with surround sound) for mobile phones document no. s16919ej1v0ds00 (1st edition) date published january 2004 n cp (k) printed in japan data sheet 2004 the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. description the pd9991 is a mobile phone ring tone generator lsi t hat includes an on-chip surround sound function. features ? pcm sound generation method provi des realistic sound reproduction ? up to 68 tones can be played at the same time, so an abundant variety of t unes can be generated and played ? implements adpcm decode functions. simult aneous playback with midi is also enabled. ? includes a high-performance d/a converter with 16-bit resolution ? supports five sampling frequency modes: 8 khz, 16 khz, 32 khz, 44.1 khz, and 48 khz (asi only) ? provides audio serial i/o interface (16 bits). the serial data input frequency is variable between 32 fs and 64 fs (during slave mode). supported formats are right-jus tified, left-justified, and iis. ? includes function for mixing pcm sound source output signals and audio serial input signals (only fs = 32 khz sampling is supported). ? includes a surround function that us es real-time processing (to produc e surround effects based on real-time processing for all sources including pcm sound sources and audio serial input). ? host cpu is connected via an 8-bit parallel interface. ? includes output control func tions for vibrator and led ? pll is built-in, so various types of input clocks can be supported. ? i/o power supply voltage: 3 v (digital pins support 3 v and 1.8 v.) ? power supply voltages: dv dd : 1.425 to 1.575 v, ev dd : 1.71 to 3.3 v, av dd : 2.85 to 3.15 v, av dd -p: 2.85 to 3.15 v ? 65-pin tape fbga package (6 6 mm body size, 0.5 ball pitch) ordering information part number package pd9991f9-ba1 65-pin tape fbga (6 6)
pd9991 data sheet s16919ej1v0ds 2 block diagram sound source lch(a) lch(b) d7 to d0 rd_b wr_b cs_b agnd led tm3, tm4 tm0 to tm2 rch lch ps clkin int_b a0 a1 vib led egnd ev dd dgnd dv dd aso lrclk bclk asi iref vref vref iref av dd lineout_l lineout_r analog volume digital volume selector/mixer rch(a) rch(b) cpu interface po0 to po3 reset_b trsck clk8k r data av dd -p agnd-p vibrator asio pll1 pll2 dvx dac remark dvx: dimagic virtualizer x
pd9991 data sheet s16919ej1v0ds 3 pin configuration ? 65-pin tape fbga (6 6) pd9991f9-ba1 k j h g f e d c b a 10 9 8 7 6 5 4 3 2 1 (bottom view) (top view) index mark pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1a shorted with 1k pin 2h clkin 6a egnd 9e reset_b 1b n.c 2j n.c 6b ps 9f d7 1c lineout_l 2k n.c 6j cs_b 9g d5 1d agnd 3a tm3 6k a0 9h d3 1e av dd 3b tm2 7a asi 9j n.c 1f lineout_r 3c n.c 7b aso 9k dv dd 1g agnd 3j po1 7j rd_b 10a shorted with 10k pin 1h agnd-p 3k po0 7k wr_b 10b n.c 1j n.c 4a rdata 8a lrclk 10c led 1k shorted with 1a pin 4b tm4 8b bclk 10d dv dd 2a n.c 4j po3 8j d1 10e int_b 2b n.c 4k po2 8k d0 10f d6 2c tm0 5a trsck 9a dv dd 10g d4 2d iref 5b clk8k 9b n.c 10h d2 2e vref 5j a1 9c ev dd 10j dgnd 2f tm1 5k dgnd 9d vib 10k shorted with 10a pin 2g av dd -p
pd9991 data sheet s16919ej1v0ds 4 pin name a0, a1: address asi: audio serial data input av dd : power supply for analog block av dd -p: power supply for pll agnd: ground for analog block agnd-p: ground for pll bclk: bit clock input/output cs_b: chip select clk8k: sync clock input for rdata clkin: clock input d0 to d7: data bus dv dd : power supply for digital block dgnd: ground for digital block ev dd : power supply for i/o pins egnd: ground for i/o pins int_b: interruption iref: current reference for dac led: led control output lineout_l: line out (l ch) lineout_r: line out (r ch) lrclk: left right clock input/output po0 to po3: peripheral output ps: parallel serial select rd_b: read rdata: record data reset_b: reset tm0 to tm2: test mode input tm3,tm4: test mode i/o trsck: clock input for rdata vib: vibration control output vref: voltage reference for dac wr_b: write
pd9991 data sheet s16919ej1v0ds 5 contents 1. pin functions .............................................................................................................. ......................8 1.1 pin configuration .......................................................................................................... ................8 1.2 explanation of pin functions ..................................... .......................................................... .......9 1.3 connection of unused pins .................................................................................................. .....13 1.4 initial state of pins ...................................................................................................... ................13 1.5 pin status................................................................................................................. ....................14 2. general description........................................................................................................ ...........16 3. host cpu interface ........................................................................................................ .............18 3.1 write access............................................................................................................... .................18 3.2 read access ................................................................................................................ ................19 4. audio serial interface .................................................................................................... ..........20 5. adpcm input interface..................................................................................................... ..........21 5.1 clk8k ...................................................................................................................... ....................21 5.2 trsck and rdata............................................................................................................ ..........21 5.2.1 serial reco rding inte rface............................................................................................... ...................21 6. registers (other than sound source regi sters)......................................................22 6.1 standby setting (stnby) .................................................................................................... .......23 6.1.1 st dig .................................................................................................................... ..........................23 6.1.2 st pll2 ................................................................................................................... .........................23 6.1.3 st pll1 ................................................................................................................... .........................23 6.1.4 stasi .................................................................................................................... ...........................23 6.1.5 staso .................................................................................................................... .........................23 6.1.6 st synth.................................................................................................................. .......................24 6.1.7 st dac .................................................................................................................... .........................24 6.1.8 st ref .................................................................................................................... .........................24 6.2 master clock switching (mclk1a, mclk1b, mclk 2a, mclk2b) ........................................25 6.2.1 mclk 1a[6:0] .............................................................................................................. ......................25 6.2.2 mclk 1b[7:0] .............................................................................................................. ......................25 6.2.3 mclk 2a[4:0] .............................................................................................................. ......................25 6.2.4 mclk 2b[7:0] .............................................................................................................. ......................25 6.3 switching/mixing of surround block input source (s lsorce) ............................................28 6.3.1 sl sorce .................................................................................................................. ......................28 6.3.2 mix...................................................................................................................... .............................28 6.4 surround on/off switching (ensrd)............................. ...........................................................28 6.4.1 ens rd[1: 0]............................................................................................................... .......................28 6.5 fs switching and bclk switching for asio (slfs) ... ............................................................29 6.5.1 fs [2:0].................................................................................................................. ............................29 6.5.2 bf s[4:0] ................................................................................................................. ..........................29 6.6 asio mode setting (slasi).................................................................................................. ......30 6.6.1 slr ...................................................................................................................... ............................30
pd9991 data sheet s16919ej1v0ds 6 6.6.2 ms ....................................................................................................................... .............................30 6.6.3 asim..................................................................................................................... ............................30 6.6.4 l rclk .................................................................................................................... ..........................30 6.7 digital volume (l) setting (daulga)............................ ............................................................ 31 6.7.1 daul ga[4:0] .............................................................................................................. ......................31 6.8 digital volume (r) setting (daurga)............................. .......................................................... 3 1 6.8.1 daurg a[4:0].............................................................................................................. ......................31 6.9 analog volume (l ch) setting (aaulga) ....................... .......................................................... 32 6.9.1 aaul ga[4:0] .............................................................................................................. ......................32 6.10 analog volume (r ch) setting (aaurga) ...................... .......................................................... 32 6.10.1 aaurg a[4:0]............................................................................................................. .......................32 6.11 vib and led settings (vib) ................................................................................................ ....... 33 6.11.1 led ..................................................................................................................... .............................33 6.11.2 vib..................................................................................................................... ...............................33 6.12 setting of general-purpose output pins (pout).... ................................................................ 33 6.12.1 pout0 to pout3.......................................................................................................... ...................33 6.13 lsi version (ver) ......................................................................................................... .............. 33 6.13.1 ver [1:0] ................................................................................................................ ...........................33 6.14 surround coefficient write register (for sp eaker) (spsrdw1, spsrdw2) ........................ 34 6.14.1 spsrdw 1[7: 0] ............................................................................................................ .....................34 6.14.2 spsrdw 2[7: 0] ............................................................................................................ .....................34 6.15 surround coefficient write register (for h eadphones) (hpsrdw1, hpsrdw2) ................ 34 6.15.1 hpsr dw1[7: 0]............................................................................................................ .....................34 6.15.2 hpsr dw2[7: 0]............................................................................................................ .....................34 6.16 surround coefficient read register (for sp eaker) (spsrdr1, spsrdr2) ......................... 35 6.16.1 spsrdr1 [7:0]............................................................................................................ ......................35 6.16.2 spsrdr2 [7:0]............................................................................................................ ......................35 6.17 surround coefficient read register (for h eadphones) (hpsrdr1, hpsrdr2) ................. 35 6.17.1 hps rdr1[7:0 ] ............................................................................................................ .....................35 6.17.2 hps rdr2[7:0 ] ............................................................................................................ .....................35 6.18 surround mode setting register (srdra)....................... ....................................................... 36 6.18.1 srdra [7:0] .............................................................................................................. ........................36 7. power startup procedure ................................................................................................... .. 37 7.1 power application sequence ................................................................................................. ... 37 7.2 shutdown sequence .......................................................................................................... ........ 37 8. power saving function ..................................................................................................... ....... 37 8.1 software power saving function (command-driven) ...... ....................................................... 37 8.2 hardware power saving function (by powering do wn the power supply)........................... 37 9. setting sequence ........................................................................................................... ............. 38 9.1 power application .......................................................................................................... ............ 38 9.2 basic sequence for switching among operation mode s...................................................... 38 9.2.1 mute ..................................................................................................................... ............................39 9.2.2 st andby .................................................................................................................. ..........................39 9.2.3 fs s witchin g ............................................................................................................. ........................39 9.2.4 path switch ing........................................................................................................... ........................39
pd9991 data sheet s16919ej1v0ds 7 9.2.5 surround switch ing ....................................................................................................... ....................40 9.2.6 set asio m ode ............................................................................................................ ....................40 9.2.7 ram access ............................................................................................................... ......................40 9.3 setting sequence example ......................................... .......................................................... .....41 9.3.1 sound sour ce-dac output.................................................................................................. ..............41 9.3.2 sound sour ce-aso output.................................................................................................. ..............41 9.3.3 asi-d ac out put ........................................................................................................... .....................42 9.3.4 asi- aso out put........................................................................................................... .....................42 9.4 relation between setting modes and internal operations (relation with synchronization clock) .......................................................................................43 10. standby mo de .............................................................................................................. ...................44 10.1 clock supply.............................................................................................................. ..................44 11. reference schematics ...................................................................................................... .........45 11.1 line out pins (lineout_l and lineout_r) ........... ...............................................................45 11.2 reference power supply voltage and current suppl y pins (vref and iref)......................45 11.3 power supply.............................................................................................................. .................46 11.4 pin outline schematics .................................................................................................... ..........47 12. electrical specifications ................................................................................................. .......48 12.1 absolute maximum ratings .................................................................................................. .....48 12.2 recommended operating conditions .............................. ........................................................48 12.3 capacitance ............................................................................................................... ..................48 12.4 dc characteristics ........................................................................................................ ..............49 12.5 ac characteristics ........................................................................................................ ..............50 12.5.1 clock ................................................................................................................... .............................50 12.5.2 re set ................................................................................................................... .............................50 12.5.3 host interf ace .......................................................................................................... .........................51 12.5.4 audio seri al inte rface .................................................................................................. ......................53 12.6 analog characteristics .................................................................................................... ...........55 12.7 mode-specific current consumption characteristics . ...........................................................56 13. package drawing ........................................................................................................... ...............57 14. recommended soldering conditions..................................................................................58
pd9991 data sheet s16919ej1v0ds 8 1. pin functions 1.1 pin configuration 8 iref 2 dgnd ps vref 3 4 2 +1.5 v +3.0 v or +1.8 v +3.0 v +3.0 v egnd agnd agnd-p vib led rdata clk8k trsck bclk lrclk asi aso cpu interface audio serial interface a/d interface vibrator control output led control output general output interrupt output for cpu int_b cs_b a0, a1 wr_b rd_b d7 to d0 pd9991 dv dd ev dd av dd av dd -p clkin reset_b clock input reset input lineout_l lineout_r tm0 to tm2 po0 to po3 tm3, tm4 voltage reference for analog block debug interface line output for amp. current reference for analog block cpu interface ps switch
pd9991 data sheet s16919ej1v0ds 9 1.2 explanation of pin functions (1) power supply pins pin name pin no. i/o function dv dd 9a, 9k, 10d ? power supply (1.5 v) for digital block be sure to connect a 0.1 f capacitor between this pin and dgnd. dgnd 5k, 10j ? ground for digital block ev dd 9c ? power supply (3 v or 1.8 v) for i/o be sure to connect a 0.1 f capacitor between this pin and egnd. use a different power supply to the analog power supply. egnd 6a ? ground for i/o av dd 1e ? power supply (3 v) for analog be sure to connect a 0.1 f capacitor between this pin and agnd. agnd 1d, 1g ? ground for analog block av dd -p 2g ? power supply (3 v) for pll be sure to connect a 0.1 f capacitor between this pin and agnd-p. agnd-p 1h ? ground for pll block vref 2e ? reference voltage for analog block be sure to connect a 0.22 f capacitor between this pin and agnd. iref 2d ? reference current for analog block be sure to connect a 56 k ? resistor between this pin and agnd. (2) clock and system control pins pin name serial no. i/o function clkin 2h input clock input (2.688 to 16.128 mhz) this is the reference clock input that is used to generate the internal master clock. be sure to input using capacitive coupling (1000 pf). reset_b 9e input hardware reset input signal. this resets the pd9991. registers are initialized to their initial values after a reset.
pd9991 data sheet s16919ej1v0ds 10 (3) host interface pins pin name pin no. i/o function a0 6k i/o host interface address a0 signal input this input pin indicates the internal register address or data during host cpu access. 1: when transferring data 0: when setting address of internal register to be accessed a1 5j input host interface address a1 signal input this input pin selects the access desti nation register during host cpu access. 1: sound source block register 0: other block register cs_b 6j input chip select input this is the input pin for the host interf ace select signal. this pin is set as active (low) while the host cpu a ccesses a host interface register. rd_b 7j input host read input this pin is set as active (low) wh ile the host cpu reads a host interface register. do not set this pin and the wr_b pin as active at the same time. wr_b 7k input host write input this pin is set as active (low) while the host cpu writes to a host interface register. do not set this pin and the rd_b pin as active at the same time. d0 to d7 8k, 8j, 10h, 9h, 10g, 9g, 10f, 9f i/o 8-bit host data bus when the host cpu accesses the pd9991, address and data i/o is performed. when the cs_b signal is inactive (hi gh), this bus is set to high impedance. int_b 10e output host interrupt output this interrupt signal is transmitted from the pd9991 to the host cpu. this is used when requesti ng transmit/receive signals during data transfer or internal status notification. remark this is used only for sound source block control.
pd9991 data sheet s16919ej1v0ds 11 (4) external led, motor control output pins pin name pin no. i/o function led 10c output external led control output (drive output: see 12.4 dc characteristics ) this is the port output pin. settings ar e entered by writing values to the port setting register from the host cpu. leave this pin open when not used. vib 9d output external motor control output (drive output: see 12.4 dc characteristics ) this is the port output pin. settings ar e entered by writing values to the port setting register from the host cpu. leave this pin open when not used. (5) audio serial interface pins pin name pin no. i/o function bclk 8b i/o bit synchronizati on clock i/o for audio serial this pin is used to input or output a clock that is 64 times the sampling frequency (8 khz, 16 khz, 32 khz, 44.1 khz, or 49 khz) that has been set as the clock for serial transfers. connect this pin to gnd when not used. lrclk 8a i/o audio serial fr ame synchronization clock i/o this pin is used to input or output a frame sync signal for serial transfers. connect this pin to gnd when not used. aso 7b output audio serial data output the audio serial data?s frame size is se t via registers. during master mode, either 64 bits or 32 bits can be select ed. during slave mode, selections can be made in 2-bit steps within a range from 32 to 64 bits. leave this pin open when not used. asi 7a input audio serial data input the audio serial data?s frame size is se t via registers. during master mode, either 64 bits or 32 bits can be select ed. during slave mode, selections can be made in 2-bit steps within a range from 32 to 64 bits. leave this pin open when not used. pull-down is performed internally. (6) adpcm interface pins pin name pin no. i/o function trsck 5a input serial clock input for adpcm recording pull-down is performed internally. leave this pin open when not used. clk8k 5b input synchronization cl ock input for adpcm recording pull-down is performed internally. leave this pin open when not used. rdata 4a input data input for adpcm recording pull-down is performed internally. leave this pin open when not used.
pd9991 data sheet s16919ej1v0ds 12 (7) dac, line out output pins pin name pin no. i/o function lineout_l 1c output sound source line out (l ch) output this pin outputs the left-channel analog signal for the pd9991?s line out function. lineout_r 1f output sound source line out (r ch) output this pin outputs the right-channel analog signal for the pd9991?s line out function. (8) general-purpose ex ternal output pins pin name pin no. i/o function po0 to po3 3k, 3j, 4k, 4j output general-purpose external output pins these pins can be used to output cont rol signals to peripheral devices. (9) test pins pin name pin no. i/o function tm0 to tm2 2c, 2f, 3b input input for test leave open or connect to gnd. pull-down is performed internally. tm3, tm4 3a, 4b i/o i/o for test leave open. ps 6b input parallel/serial setting input (for testing) this pin should be either le ft open or connected to gnd. pull-down is performed internally.
pd9991 data sheet s16919ej1v0ds 13 1.3 connection of unused pins it is recommended to connect the unused pins as shown in the table below. pin name i/o recommended connection vib output leave open. led output leave open. lrclk i/o connect to gnd. bclk i/o connect to gnd. asi input leave open. aso output leave open. tm0 to tm2 input leave open. tm3, tm4 i/o leave open. trsck input leave open. clk8k input leave open. rdata input leave open. po0 to po3 output leave open. 1.4 initial state of pins pin name i/o during reset after reset vib output bus hold low-level output led output bus hold low-level output int_b output high-level output high-level output aso output hi-z hi-z bclk i/o hi-z input lrclk i/o hi-z input tm3, tm4 i/o hi-z low-level output po0 to po3 output hi-z low-level output d7 to d0 i/o hi-z input
pd9991 data sheet s16919ej1v0ds 14 1.5 pin status the pd9991?s pin status table is shown below. (1/2) standby status reset status (reset_b = low) pin no. i/o analog/ digital pin name control signal pin status control signal pin status after reset 2f input digital tm1 none input none input input 2c input digital tm0 none input none input input 1c output analog lineout_l stdac hi-z stdac hi-z hi-z 1d ? analog agnd ? ? ? ? ? 2d output analog iref stre f hi-z stref hi-z hi-z 2e output analog vref sterf hi-z sterf hi-z hi-z 1e ? analog av dd ? ? ? ? ? 1f output analog lineout_r st dac hi-z stdac hi-z hi-z 1g ? analog agnd ? ? ? ? ? 1h ? analog agnd-p ? ? ? ? ? 2h input analog clkin stpll1& 2 hi-z stpll1&2 hi-z hi-z 2g ? analog av dd -p ? ? ? ? ? 3k i/o digital po0 none note 1 reset_b bus hold low output note2 3j i/o digital po1 none note 1 reset_b bus hold low output note2 4k i/o digital po2 none note 1 reset_b bus hold low output note2 4j i/o digital po3 none note 1 reset_b bus hold low output note2 5k ? digital dgnd ? ? ? ? ? 5j input digital a1 none input none input input 6k i/o digital a0 none input none input input 9k ? digital dv dd ? ? ? ? ? 6j input digital cs_b none input none input input 7k input digital wr_b none input none input input 7j input digital rd_b none input none input input 8k i/o digital d0 none input reset_b hi-z input 8j i/o digital d1 none input reset_b hi-z input 10h i/o digital d2 none input reset_b hi-z input 9h i/o digital d3 none input reset_b hi-z input 10g i/o digital d4 none input reset_b hi-z input 9g i/o digital d5 none input reset_b hi-z input 10f i/o digital d6 none input reset_b hi-z input 9f i/o digital d7 none input reset_b hi-z input 10j ? digital dgnd ? ? ? ? ? 10e output digital int_b none output reset_b high output high output 9e input digital reset_b none input none input input 10d ? digital dv dd ? ? ? ? ? 9d output digital vib none note 3 reset_b bus hold low output note2 10c output digital led none note 3 reset_b bus hold low output note2 notes 1. differs according to register setting. see 6.12 setting of general-purpose output pins . 2. registers are reset to initial values, so signals with levels corresponding to initial values are output. 3. differs according to register setting. see 6.11 vib and led settings .
pd9991 data sheet s16919ej1v0ds 15 (2/2) standby status reset status (reset_b = low) pin no. i/o analog/ digital pin name control signal pin status control signal pin status after reset 9c ? digital ev dd ? ? ? ? ? 8a i/o digital lrclk stasi, staso note reset_b hi-z input 8b i/o digital bclk stasi, staso note reset_b hi-z input 7a input digital asi stasi, staso note none input input 7b output digital aso stasi, staso note reset_b hi-z hi-z 6a ? digital egnd ? ? ? ? ? 9a ? digital dv dd ? ? ? ? ? 6b input digital ps none input none input input 5a input digital trsck none input none input input 5b input digital clk8k none input none input input 4a input digital rdata none input none input input 4b i/o digital tm4 stdig low output reset_b hi-z low output 3a i/o digital tm3 stdig low output reset_b hi-z low output 3b input digital tm2 none input none input input note for description of the status of the lrclk, bclk, asi, and aso pins during standby mode, see table 1-1 . table 1-1. pin status in asio block ms = 0 (slave) ms = 1 (master) [stasi, staso] [stasi, staso] pin no. i/o analog/ digital pin name [0, 0] [0, 1] [1, 0] [1, 1] [0, 0] [0, 1] [1, 0] [1, 1] 8a i/o digital lrclk input note input input input fixed to low output output output 8b i/o digital bclk input note input input input fixed to low output output output 7a input digital asi invalid invalid input input invalid invalid input input 7b output digital aso hi-z output hi -z output hi-z output hi-z output note fixed to low level internally remarks 1. ms is bit d2 in the slasi register (08h). see 6.6 asio mode setting . 2. stasi and staso are bits d4 and d3 in the stnby register (00h). see 6.1 standby setting .
pd9991 data sheet s16919ej1v0ds 16 2. general description figure 2-1. block diagram sound source lch(a) lch(b) d7 to d0 rd_b wr_b cs_b agnd led tm3, tm4 tm0 to tm2 rch lch ps clkin int_b a0 a1 vib led egnd ev dd dgnd dv dd aso lrclk bclk asi iref vref vref iref av dd lineout_l lineout_r analog volume digital volume selector/mixer rch(a) rch(b) cpu interface po0 to po3 reset_b trsck clk8k r data av dd -p agnd-p vibrator asio pll1 pll2 dvx dac (1) pll1, pll2 (clkin pin) clock input in the range from 2. 688 to 16.128 mhz is supported. in this block, when a clock with a frequency in this range is input, it is multiplied by the pll to generate the fixed frequency clock that is required internally. pll1 generates the clock signals required by all blocks except for the sound source block, and pll2 generates t he clock signal for the sound source block. (2) cpu interface this connects to the host cpu via an 8-bit parallel interface. (3) vibrator, led control output port this is an output port for the leds and vibrator. (4) pcm sound source block a pcm sound source for generation of up to 64 simult aneous tones is on chip, al ong with a sequencer. the sampling frequency is 32 khz. the adpcm?s playback function is also on chip. the sampling frequency options are 8 khz 4 channels, 16 khz 2 channels, and 32 khz 1 channel.
pd9991 data sheet s16919ej1v0ds 17 (5) audio serial i/o interface this is an i/o interface for external audio data. five sampling frequency modes are supported: 8 khz, 16 khz, 32 khz, 44.1 khz, and 48 khz (initial value is 32 khz). the serial data input frequency is variable between 32 fs and 64 fs (during slave mode). (6) selector/mixer this block is used to switch among or mix sound sources and audio serial input. (7) dvx (surround) this block performs real-time surround processing. (8) dac this block converts digital signals (from sound sources or audio serial input) to analog signals. this dac (d/a converter) is a high-performance stereo dac with 16-bit resolution.
pd9991 data sheet s16919ej1v0ds 18 3. host cpu interface the access method from the host cpu interface is described below. 3.1 write access during write access, data is written to the pd9991 from the system. the write a ccess timing is shown in figures 3-1 and 3-2. ? a0 is used to distinguish between address write cycles and data write cycles. ? a1 is used to distinguish between register access fo r sound sources and register access for other purposes (0: other than sound source, 1: sound source). ? in the address write cycle, the data write address is assigned to bits d7 to d0. ? operation is based on detec tion of the rising edge of wr_b by the system clock. caution be sure to fix the rd_b pin to high level during address write cycles and data write cycles. figure 3-1. write access (single access) cs_b a0, a1 wr_b rd_b d7 to d0 address write cycle data write cycle t suaw t haw t wwr t rcwr t sud1 t hd1 write address write data d.c d.c h d.c next address figure 3-2. write access (continuous access) cs_b a0, a1 wr_b rd_b d7 to d0 write access continuous write access write address write address write data d.c d.c d.c write data d.c write data d.c d.c h remark set the cs_b pin to low level during the write period. it is not necessary to always set the cs_b pin to low level during continuous write access. d.c: don?t care
pd9991 data sheet s16919ej1v0ds 19 3.2 read access during read access, data is read from the system by the pd9991. the read access timing is shown below. ? a0 is used to distinguish between address write cycles and data read cycles. ? a1 is used to distinguish between register access fo r sound sources and register access for other purposes (0: other than sound source, 1: sound source). ? operation is based on detecti on of the rising edge of wr_b and rd_b by the system clock. ? in the address write cycle, the data write address is assigned to bits d7 to d0. figure 3-3. read access (single access) cs_b a0, a1 wr_b rd_b d7 to d0 address write cycle data read cycle read address read data d.c d.c d.c next address t har t suar t wrd t rcrd t ddo t accdo figure 3-4. read access (continuous access) cs_b a0, a1 wr_b rd_b d7 to d0 read access continuous read access read address read address read data d.c read data d.c read data d.c d.c d.c d.c remark set the cs_b pin to low level during the read period. it is not necessary to always set the cs_b pin to low level during continuous read access. d.c: don?t care
pd9991 data sheet s16919ej1v0ds 20 4. audio serial interface when lrclk = 0 in the slasi register (08h), l-ch data is assigned during the high-level period of lrclk and r-ch data is assigned during the low-level period of lrclk. fo r iis format, this is reversed, in which case lrclk = 1 should be set. within each of these periods, the fo rmat can be switched among right-justifi ed, left-justified, and iis format. selection of master mode or slave mode is also enabled. the number of data bits per frame can be set via the bfs[4:0] bits in the sfsl register (07h). the serial input/output timing is shown in figures 4-1 to 4-3. figure 4-1. right-justified format lrclk bclk aso asi 1/fs l ch r ch d2 d1 d0 d15 d14 d2 d1 d0 d15 d14 d2 d1 d0 d2 d1 d0 d15 d14 d15 d14 d2 d1 d0 d2 d1 d0 figure 4-2. left-justified format lrclk bclk aso asi 1/fs l ch r ch d1 d0 d15 d14 d2 d1 d0 d15 d14 d2 d1 d0 d2 d1 d0 d15 d14 d15 d14 d1 d0 d2 d1 d0 d15 d14 d15 d14 figure 4-3. iis format lrclk bclk aso asi 1/fs l ch r ch d1 d0 d15 d14 d1 d0 d15 d14 d1 d0 d1 d0 d15 d14 d15 d14 d1 d0 d1 d0 d15 d15 remarks 1. the iis format is left-justified wit h one empty bit and sets l-ch to low level and r-ch to high level. do not specify other settings when selecting iis m ode (asim = 1 in slasi register (08h)). when selecting lr mode (asim = 0 in sl asi register (08h)), left or right justification can be selected in combination with normal or reversed left-right format. 2. the number of data bits per frame can be set via the bfs[4:0] bits in t he sfsl register (07h). during master mode, either 64 bits or 32 bits can be selected. during slave mode, any value between 32 bits and 64 bits can be selected in two-bit increments. after a reset is cleared, the default frame configur ation setting is 64 bits total (32 bits for l-ch and 32 bits for r-ch).
pd9991 data sheet s16919ej1v0ds 21 5. adpcm input interface 5.1 clk8k this is the input pin for the clock signal used for exter nal 8 khz synchronization when recording. during playback, this clock signal is generated based on a 32 khz signal generated in the pd9991, and during recording this signal is generated based on an 8 khz clock signal input from an external source. caution if an 8 khz synchronization clock signal is not being input from an external source during recording, the recorded data cannot be saved. figure 5-1. synchronization during adpcm recording 8 khz signal internal 32 khz signal 32 khz signal is auto-generated according to clock control settings standby for 8 khz signal synchronization at 8 khz 5.2 trsck and rdata the adpcm input interface is an external synchronous se rial interface used for input and output of linear pcm data. 5.2.1 serial recording interface the timing of the external synchronous serial interface is shown below. figure 5-2. timing of external synchronous serial interface 3.9 s 0.5 s (min.) 0.5 s (min.) trsck (256 khz) clk8k (8 khz) rdata d0 d14 d15 start (i_clk8k) is detected during one or two system clock cycles internal data is latched during one or two system clock cycles i_clk8k's falling edge is "don't care" transfer of adpcm recorded data is performed in synchronization with an external 8 khz sync signal and an external serial clock. latching of data is performed at the falling edge of the serial clock and data is latched msb first in 16-bit segments. in the case of 16-bit linear pcm data (t wo?s complement format), all 16 bits are valid, but in the case of -law 8-bit pcm data, the higher 8 bits are ignor ed and only the lower 8 bits contain valid data. caution input to the clk8k pin is detected only at the rising edge.
pd9991 data sheet s16919ej1v0ds 22 6. registers (other than sound source registers) registers other than sound source registers are described below. caution information on sound source registers will be di sclosed only to parties that have signed an nda (non disclosure agreement). table 6-1. list of control registers address r/w d7 d6 d5 d4 d3 d2 d1 d0 initial value control description register name 00h r/w stdig stpll2 stpll1 stasi staso stsyn th stdac stref 00h lsi standby setting stnby 01h r/w ? mclk1a[6:0] 1ch mast er clock setting 1 mclk1a 02h r/w mclk1b[7:0] 80h master clock setting 1 mclk1b 03h r/w ? ? ? mclk2a[4:0] 02h master clock setting 2 mclk2a 04h r/w mclk2b[7:0] 27h master clock setting 2 mclk2b 05h r/w ? ? ? ? ? ? mix slsorce 00h source input and mixing settings slsorce 06h r/w ? ? ? ? ? ? ensr d[1:0] 00h surround ensrd 07h r/w bfs[4:0] fs[2:0] 00h frequency switching and asio bclk setting slfs 08h r/w ? ? ? ? slr ms asim lrclk 00h asi setting slasi 09h r/w ? ? ? daulga[4:0] 02h digital volume (l) set value daulga 0ah r/w ? ? ? daurga[4:0] 02h digital volume (r) set value daurga 0bh r/w ? ? ? aaulga[4:0] 1fh analog volume (l) set value aaulga 0ch r/w ? ? ? aaurga[4:0] 1fh analog volume (r) set value aaurga 0dh r/w ? ? ? ? ? ? vib led 00h led and vib output settings vib 0eh r/w ? ? ? ? pout3 pout2 pout1 po ut0 00h user port output setting pout 3fh r ? ? ? ? ? ? ver[1:0] note lsi version ver 40h w spsrdw1[7:0] u ndefined sp surr ound coefficient 1 spsrdw1 41h w spsrdw2[7:0] u ndefined sp surr ound coefficient 2 spsrdw2 42h w hpsrdw1[7:0] undefined hp surr ound coefficient 1 hpsrdw1 43h w hpsrdw2[7:0] undefined hp surr ound coefficient 2 hpsrdw2 44h r spsrdr1[7:0] 00h sp surround coefficient 1 spsrdr1 45h r spsrdr2[7:0] 00h sp surround coefficient 2 spsrdr2 46h r hpsrdr1[7:0] 00h hp surround coefficient 1 hps rdr1 47h r hpsrdr2[7:0] 00h hp surround coefficient 2 hps rdr2 48h r/w srdra[7:0] 00h surround mode setting srdra note differs according to the lsi version. remark bits marked with ? ? ? are ?don?t care? bits.
pd9991 data sheet s16919ej1v0ds 23 6.1 standby setting (stnby) this register sets standby mode. address: 00h, register name: stnby, block: general, access: r/w, initial value: 00h d7 d6 d5 d4 d3 d2 d1 d0 stdig stpll2 stpll1 stasi staso stsynth stdac stref 6.1.1 stdig data mode initial value description 0 standby standby for digital block 1 on 0 normal operation 6.1.2 stpll2 data mode initial value description 0 standby standby for pll2 1 on 0 normal operation remark during pll2 standby mode (power down ), the pll2 output clock is stopped. 6.1.3 stpll1 data mode initial value description 0 standby standby for pll1 1 on 0 normal operation remark during pll1 standby mode (power down ), the pll1 output clock is stopped. 6.1.4 stasi data mode initial value description 0 standby standby for audio serial interface input (asi) 1 on 0 normal operation 6.1.5 staso data mode initial value description 0 standby standby for audio serial interface output (aso) 1 on 0 normal operation caution lrclk and bclk operate in standby mode only when both the stasi and staso bits have been set for standby. for details, see table 1-1. pin status in asio block.
pd9991 data sheet s16919ej1v0ds 24 6.1.6 stsynth data mode initial value description 0 standby standby for sound source block (synthesizer) 1 on 0 normal operation 6.1.7 stdac data mode initial value description 0 standby standby for dac block note 1 on 0 normal operation note this standby signal is shared by the dac analog block and the analog volume function. 6.1.8 stref data mode initial value description 0 standby standby for voltage/current reference block note 1 on 0 normal operation note this is the standby signal for the analog block?s voltage reference and current reference sources.
pd9991 data sheet s16919ej1v0ds 25 6.2 master clock switching (mclk1 a, mclk1b, mclk2a, mclk2b) these registers set master clock 1 and master clock 2. address: 01h, register name: mclk1a, block: pll1, access: r/w, initial value: 1ch d7 d6 d5 d4 d3 d2 d1 d0 ? mclk1a[6:0] address: 02h, register name: mclk1b, block: pll1, access: r/w, initial value: 80h d7 d6 d5 d4 d3 d2 d1 d0 mclk1b[7:0] address: 03h, register name: mclk2a, block: pll2, access: r/w, initial value: 02h d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? mclk2a[4:0] address: 04h, register name: mclk2b, block: pll2, access: r/w, initial value: 27h d7 d6 d5 d4 d3 d2 d1 d0 mclk2b[7:0] 6.2.1 mclk1a[6:0] data mode initial value description mclk1a[6:0] 1ch sets pll1, used to generate the audio master clock. 6.2.2 mclk1b[7:0] data mode initial value description mclk1b[7:0] 80h sets pll1, used to generate the audio master clock. 6.2.3 mclk2a[4:0] data mode initial value description mclk2a[4:0] 02h sets pll2, used to generate the sound source master clock. 6.2.4 mclk2b[7:0] data mode initial value description mclk2b[7:0] 27h sets pll2, used to generate the sound source master clock. master clock setting examples are shown below.
pd9991 data sheet s16919ej1v0ds 26 (1) audio master clock setting this sets the clock frequency supplied to all blocks except the sound source block. be sure to set the mclk1a and mclk1b registers according to the input clock frequency and sampling frequency. the input clock signal is first divided by the value set to the mclk1a register and is then multiplied by the value set to the mclk1b register. mclk1a mclk1b error clkin input frequency [mhz] (dec) (hex) (dec) (hex) sampling frequency fs [khz] internal sampling frequency fsi [khz] ? f [hz] [%] master clock frequency for audio [mhz] 2.688 20 14 168 a8 44.1 44.1000 0.00 0.0000 22.57920 5.376 40 28 168 a8 44.1 44.1000 0.00 0.0000 22.57920 12.000 76 4c 143 8f 44.1 44.0995 ?0.49 ?0.0011 22.57895 12.600 77 4d 138 8a 44.1 44.1051 5.11 0.0116 22.58182 13.000 76 4c 132 84 44.1 44.0995 ?0.49 ?0.0011 22.57895 14.400 125 7d 196 c4 44.1 44.1000 0.00 0.0000 22.57920 16.128 120 78 168 a8 44.1 44.1000 0.00 0.0000 22.57920 2.688 14 0e 128 80 48 48.0000 0.00 0.0000 24.57600 5.376 28 1c 128 80 48 48.0000 0.00 0.0000 24.57600 12.000 62 3e 127 7f 48 48.0091 9.07 0.0189 24.58065 12.600 81 51 158 9e 48 48.0035 3.47 0.0072 24.57778 13.000 64 40 121 79 48 48.0042 4.15 0.0086 24.57813 14.400 75 4b 128 80 48 48.0000 0.00 0.0000 24.57600 16.128 84 54 128 80 48 48.0000 0.00 0.0000 24.57600 2.688 14 0e 128 80 32 32.0000 0.00 0.0000 24.57600 5.376 28 1c 128 80 32 32.0000 0.00 0.0000 24.57600 12.000 62 3e 127 7f 32 32.0060 6.05 0.0189 24.58065 12.600 81 51 158 9e 32 32.0023 2.31 0.0072 24.57778 13.000 64 40 121 79 32 32.0028 2.77 0.0086 24.57813 14.400 75 4b 128 80 32 32.0000 0.00 0.0000 24.57600 16.128 84 54 128 80 32 32.0000 0.00 0.0000 24.57600 2.688 14 0e 128 80 8 8.0000 0.00 0.0000 24.57600 5.376 28 1c 128 80 8 8.0000 0.00 0.0000 24.57600 12.000 62 3e 127 7f 8 8.0015 1.51 0.0189 24.58065 12.600 81 51 158 9e 8 8.0006 0.58 0.0072 24.57778 13.000 64 40 121 79 8 8.0007 0.69 0.0086 24.57813 14.400 75 4b 128 80 8 8.0000 0.00 0.0000 24.57600 16.128 84 54 128 80 8 8.0000 0.00 0.0000 24.57600 2.688 14 0e 128 80 16 16.0000 0.00 0.0000 24.57600 5.376 28 1c 128 80 16 16.0000 0.00 0.0000 24.57600 12.000 62 3e 127 7f 16 16.0030 3.02 0.0189 24.58065 12.600 81 51 158 9e 16 16.0012 1.16 0.0072 24.57778 13.000 64 40 121 79 16 16.0014 1.38 0.0086 24.57813 14.400 75 4b 128 80 16 16.0000 0.00 0.0000 24.57600 16.128 84 54 128 80 16 16.0000 0.00 0.0000 24.57600
pd9991 data sheet s16919ej1v0ds 27 (2) sound source master clock setting this sets the frequency of the clock to be supplied to the sound source block. be sure to set values in the mclk2a and mclk2b registers according to the input cl ock frequency. the input clock signal is first divided by the value set to the mclk2a register and is then multiplied by the value set to the mclk2b register. mclk2a mclk2b error clkin input frequency [mhz] (dec) (hex) (dec) (hex) sampling frequency fs [khz] internal sampling frequency fsi [khz] ? f [hz] [%] master clock frequency for sound source [mhz] 2.688 1 01 41 29 32 32.0000 0.00 0.0000 55.10400 5.376 2 02 41 29 32 32.0000 0.00 0.0000 55.10400 12.000 5 05 46 2e 32 32.0000 0.00 0.0000 55.20000 12.600 5 05 44 2c 32 32.0092 9.24 0.0289 55.44000 13.000 5 05 42 2a 32 32.0047 4.69 0.0147 54.60000 14.400 6 06 46 2e 32 32.0000 0.00 0.0000 55.20000 16.128 6 06 41 29 32 32.0000 0.00 0.0000 55.10400
pd9991 data sheet s16919ej1v0ds 28 6.3 switching/mixing of surround bl ock input source (slsorce) this register is used to set switching and mixing of the surround block?s input source. address: 05h, register name: slsorce, block: selector, access: r/w, initial value: 00h d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? ? ? ? mix slsorce 6.3.1 slsorce data mode initial value description 0 synth select input from sound source (synthesizer) 1 asi 0 select input from audio serial interface input (asi) 6.3.2 mix data mode initial value description 0 path selection only one path is used for output from either the sound source or asi (set via slsorce). 1 mixing 0 mixes sound source and asi signals (slsorce setting is invalid). cautions 1. mixing mode is supporte d only when the sampling frequency is 32 khz. consequently, when setting mix = 1, be sure to set the fs[2:0] bits of the slfs register (07h) to 000b (see 6.5 fs switching and bclk switching for asio (slfs)). 2. if the sum of the sound source and the as i signal exceeds the full scale, the output signal will be clipped. 3. when setting the mix bit to 1 while asio is in slave mode (ms bit of slasi register = 1 (08h)), be sure to set the stasi bit of the slasi regi ster (08h) to 1 and input bclk and lrclk. when stopping the asi input and using the sound source only, retain the settings of ms = 1, mix = 1, and stasi = 1 or set mix = 0 and slsorce = 0. 6.4 surround on/off switching (ensrd) this switches the surround function on and off. address: 06h, register name: ensrd, block: dvx, access: r/w, initial value: 00h d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? ? ? ? ensrd[1:0] 6.4.1 ensrd[1:0] data mode initial value description 00b off surround processing is not performed. 01b spk the coefficient set to the sp?s coefficient setting registers (addresses 40h and 41h) is used to perform surround processing. 10b hp the coefficient set to the hp?s c oefficient setting regist ers (addresses 42h and 43h) is used to perform surround processing. 11b ? 00b setting prohibited caution reading or writing of the surround coeffi cient is enabled only when ensrd[1:0] = 00b.
pd9991 data sheet s16919ej1v0ds 29 6.5 fs switching and bclk switching for asio (slfs) this sets the asi?s sampling rate and the frequency of bclk. address: 07h, register name: slfs, block: asio, access: r/w, initial value: 00h d7 d6 d5 d4 d3 d2 d1 d0 bfs[4:0] fs[2:0] 6.5.1 fs[2:0] data mode initial value description 000b 32 khz sets asio?s sampling rate as 32 khz. 001b 44.1 khz sets asio?s sampling rate as 44.1 khz. 010b 48 khz sets asio?s sampling rate as 48 khz. 100b 8 khz sets asio?s sampling rate as 8 khz. 101b 16 khz 000b sets asio?s sampling rate as 16 khz. caution be sure to set this in tandem with the master clock setting (set for each sampling frequency). do not set any data that is not shown above. when setting a sampling rate of 8 khz or 16 khz, also set data 80h at address f3h. 6.5.2 bfs[4:0] data mode initial value description 00h 64 fs sets 64 fs as bclk fr equency (can be set during master mode). 01h 62 fs sets 62 fs as bclk frequency. 02h 60 fs sets 60 fs as bclk frequency. 03h 58 fs sets 58 fs as bclk frequency. 04h 56 fs sets 56 fs as bclk frequency. 05h 54 fs sets 54 fs as bclk frequency. 06h 52 fs sets 52 fs as bclk frequency. 07h 50 fs sets 50 fs as bclk frequency. 08h 48 fs sets 48 fs as bclk frequency. 09h 46 fs sets 46 fs as bclk frequency. 0ah 44 fs sets 44 fs as bclk frequency. 0bh 42 fs sets 42 fs as bclk frequency. 0ch 40 fs sets 40 fs as bclk frequency. 0dh 38 fs sets 38 fs as bclk frequency. 0eh 36 fs sets 36 fs as bclk frequency. 0fh 34 fs sets 34 fs as bclk frequency. 10h 32 fs 00h sets 32 fs as bclk frequency (can be set during master mode). caution during master mode (ms = 1), only 64 fs (00h) or 32 fs (10h) can be set. if any other value is set, 64 fs (the initial value) will be selected. during slave mode (ms = 0), any sampling freque ncy from 32 fs to 64 fs can be set in 2 fs increments.
pd9991 data sheet s16919ej1v0ds 30 6.6 asio mode setting (slasi) this specifies the asi setting as shown below. address: 08h, register name: slasi, block: asio, access: r/w, initial value: 00h d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? ? slr ms asim lrclk 6.6.1 slr data mode initial value description 0 sr right-justified format 1 sl 0 left-justified format 6.6.2 ms data mode initial value description 0 slave slave mode 1 master 0 master mode caution during slave mode, external clock input is requi red. for description of the pin status of the asio block during various modes, see 1.5 pin status. 6.6.3 asim data mode initial value description 0 lr lr mode 1 iis 0 iis mode (in this case, the slr bit is a ?don?t care? bit). 6.6.4 lrclk data mode initial value description 0 lch when lrclk is at high level, this specifies l channel data. 1 rch 0 when lrclk is at high level, this specifies r channel data. caution be sure to set lrclk = 1 when iis mode is selected.
pd9991 data sheet s16919ej1v0ds 31 6.7 digital volume (l) setting (daulga) this sets the l channel?s digital gain. address: 09h, register name: daulga, block: dig ital volume, access: r/w, initial value: 02h d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? daulga[4:0] 6.7.1 daulga[4:0] data mode initial value description daulga[4:0] 02h sets digital gain (l ch) 6.8 digital volume (r) setting (daurga) this sets the r channel?s digital gain. address: 0ah, register name: daurga, block: dig ital volume, access: r/w, initial value: 02h d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? daurga[4:0] 6.8.1 daurga[4:0] data mode initial value description daurga[4:0] 02h sets digital gain (r ch) table 6-1. digital volume (5-bit non-linear) gain daulga[4:0]/ daurga[4:0] gain daulga[4:0]/ daurga[4:0] +12 db 00h ?30 db 0ch +6 db 01h ?33 db 0dh 0 db 02h (initial value) ?36 db 0eh ?3 db 03h ?39 db 0fh ?6 db 04h ?42 db 10h ?9 db 05h ?45 db 11h ?12 db 06h ?48 db 12h ?15 db 07h ?51 db 13h ?18 db 08h ?54 db 14h ?21 db 09h ?57 db 15h ?24 db 0ah ?60 db 16h ?27 db 0bh mute 17h
pd9991 data sheet s16919ej1v0ds 32 6.9 analog volume (l ch) setting (aaulga) this sets the l channel?s analog gain. address: 0bh, register name: aaulga, block: analog volume, access: r/w, initial value: 1fh d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? aaulga[4:0] 6.9.1 aaulga[4:0] data mode initial value description aaulga[4:0] 1fh sets analog gain (l ch) 6.10 analog volume (r ch) setting (aaurga) this sets the r channel?s analog gain. address: 0ch, register name: aaurga, block: analog volume, access: r/w, initial value: 1fh d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? aaurga[4:0] 6.10.1 aaurga[4:0] data mode initial value description aaurga[4:0] 1fh sets analog gain (r ch) table 6-2. analog volume (5-bit linear) gain aaulga[4:0] / aaurga[4:0] gain aaulga[4:0] / aaurga[4:0] 0 db 00h ?24 db 10h ?1.5 db 01h ?25.5 db 11h ?3 db 02h ?27 db 12h ?4.5 db 03h ?28.5 db 13h ?6 db 04h ?30 db 14h ?7.5 db 05h ?31.5 db 15h ?9 db 06h ?33 db 16h ?10.5 db 07h ?34.5 db 17h ?12 db 08h ?36 db 18h ?13.5 db 09h ?37.5 db 19h ?15 db 0ah ?39 db 1ah ?16.5 db 0bh ?40.5 db 1bh ?18 db 0ch ?42 db 1ch ?19.5 db 0dh ?43.5 db 1dh ?21 db 0eh ?45 db 1eh ?22.5 db 0fh mute 1fh (initial value)
pd9991 data sheet s16919ej1v0ds 33 6.11 vib and led settings (vib) this register is used to control t he output port for the vibrator and led. address: 0dh, register name: vib, block: a nalog volume, access: r/w, initial value: 00h d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? ? ? ? vib led 6.11.1 led data mode initial value description 0 off low-level output from led pin 1 on 0 high-level output from led pin 6.11.2 vib data mode initial value description 0 off low-level output from vib pin 1 on 0 high-level output from vib pin caution for both led and vib, the register value is output to the pd9991?s pins. 6.12 setting of general-purpose output pins (pout) this sets the output level for the general -purpose output pins (pins po0 to po3). address: 0eh, register name: pout, block: po, access: r/w, initial value: 00h d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? ? pout3 pout2 pout1 pout0 6.12.1 pout0 to pout3 data mode initial value description 0 low low-level output from co rresponding pins po0 to po3. 1 high 0 high-level output from corre sponding pins po0 to po3. caution when the digital block is in standby mode (address 00h, stdig = 0), output from pins po0 to po3 is held at the level set vi a pout0 to pout3. for details, see table 1-1 pin status in asio block in 1.5 pin status. 6.13 lsi version (ver) this displays the lsi?s version information. address: 3fh, register name: ver, block: other, a ccess: r, initial value: differs depending on lsi version d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? ? ? ? ver[1:0] 6.13.1 ver[1:0] data mode initial value description ver[1:0] ? lsi version
pd9991 data sheet s16919ej1v0ds 34 6.14 surround coefficient write register (for speaker) (spsrdw1, spsrdw2) this register is used to write t he surround coefficient for the speaker. address: 40h, register name: spsrdw1, block: dvx, access: w, initial value: undefined d7 d6 d5 d4 d3 d2 d1 d0 spsrdw1[7:0] address: 41h, register name: spsrdw2, block: dvx, access: w, initial value: undefined d7 d6 d5 d4 d3 d2 d1 d0 spsrdw2[7:0] 6.14.1 spsrdw1[7:0] data mode initial value description spsrdw1[7:0] undefined surround coefficient setting register 1 (for speaker) 6.14.2 spsrdw2[7:0] data mode initial value description spsrdw2[7:0] undefined surround coefficient setting register 2 (for speaker) 6.15 surround coefficient write register (f or headphones) (hpsrdw1, hpsrdw2) this register is used to write the surround coefficient for the headphones. address: 42h, register name: hpsrdw1, bloc k: dvx, access: w, initial value: undefined d7 d6 d5 d4 d3 d2 d1 d0 hpsrdw1[7:0] address: 43h, register name: hpsrdw2, bloc k: dvx, access: w, initial value: undefined d7 d6 d5 d4 d3 d2 d1 d0 hpsrdw2[7:0] 6.15.1 hpsrdw1[7:0] data mode initial value description hpsrdw1[7:0] undefined surround coefficient setting register 1 (for headphones) 6.15.2 hpsrdw2[7:0] data mode initial value description hpsrdw2[7:0] undefined surround coefficient setting register 2 (for headphones) cautions 1. to access the surround coe fficient write registers (40h, 41h, 42h, and 43h), first write to the surround address setting register, then continuously write data 192 times. writing the data 192 times sets values to the ram that stores internal surround coefficients. 2. the surround coefficient must be written us ing continuous write access. even if the cs_b pin goes to high level during the continuous wr ite operation and the cpu control switches to another device, the surround coefficient is written without any prob lem if it is accessed following the previous write operation wh en the cs_b pin goes to low level. 3. if an interrupt (int_b) occurs while data is being written continuously , start over by writing the surround address setting register again. 4. reading and writing of surround coefficien ts are enabled only when ensrd[1:0] = 00b.
pd9991 data sheet s16919ej1v0ds 35 6.16 surround coefficient read register (for speaker) (spsrdr1, spsrdr2) this register is used to read the surround coefficient for the speaker. address: 44h, register name: spsrdr1, block: dvx, access: r, initial value: 00h d7 d6 d5 d4 d3 d2 d1 d0 spsrdr1[7:0] address: 45h, register name: spsrdr2, block: dvx, access: r, initial value: 00h d7 d6 d5 d4 d3 d2 d1 d0 spsrdr2[7:0] 6.16.1 spsrdr1[7:0] data mode initial value description spsrdr1[7:0] 00h surround coefficient setting register 1 (for speaker) 6.16.2 spsrdr2[7:0] data mode initial value description spsrdr2[7:0] 00h surround coefficient setting register 2 (for speaker) 6.17 surround coefficient read register (for headphones) (hpsrdr1, hpsrdr2) this register is used to read t he surround coefficient for the headphones. address: 46h, register name: hpsrdr1, block: dvx, access: r, initial value: 00h d7 d6 d5 d4 d3 d2 d1 d0 hpsrdr1[7:0] address: 47h, register name: hpsrdr2, block: dvx, access: r, initial value: 00h d7 d6 d5 d4 d3 d2 d1 d0 hpsrdr2[7:0] 6.17.1 hpsrdr1[7:0] data mode initial value description hpsrdr1[7:0] 00h surround coefficient setting register 1 (for headphones) 6.17.2 hpsrdr2[7:0] data mode initial value description hpsrdr2[7:0] 00h surround coefficient setting register 2 (for headphones) cautions 1. to access the surround coe fficient read registers (44h, 45h, 46h, and 47h), first write to the surround address setting register, then continuously read data 192 times. reading the data 192 times sets values to the ram that stores internal surround coefficients. 2. the surround coefficient must be read usi ng continuous read access. even if the cs_b pin goes to high level during the continuous read operation and the cpu control switches to another device, the surround coefficient is read without any problem if it is accessed following the previous read operation wh en the cs_b pin goes to low level. 3. if an interrupt (int_b) occurs while data is being read continuously, start over by writing the surround address setting register again. 4. reading and writing of surround coefficien ts are enabled only when ensrd[1:0] = 00b.
pd9991 data sheet s16919ej1v0ds 36 6.18 surround mode setting register (srdra) this register sets the mode for r eading/writing of surround coefficients. address: 48h, register name: srdra, block: dvx, access: r/w, initial value: 00h d7 d6 d5 d4 d3 d2 d1 d0 srdra[7:0] 6.18.1 srdra[7:0] data mode initial value description srdra[7:0] 00h sets access to surround register caution set srdra[7:0] to 00h.
pd9991 data sheet s16919ej1v0ds 37 7. power startup procedure the pd9991 includes four power supply units: the internal digital logic block power supply (dv dd ), pll1/pll2 power supply (av dd -p), internal analog circuit?s power supply (av dd ), and the i/o circuit?s power supply (ev dd ). 7.1 power application sequence <1> with the reset_b pin set to low level, turn on the power supply units (dv dd , av dd , av dd -p, and ev dd ). we recommend turning on all four of these units at the same time. <2> wait until the power supply voltage reaches the specified voltage value. <3> cancel the hardware reset. to cancel, set the reset_b pin to high level. 7.2 shutdown sequence <1> with the reset_b pin set to low level, turn off the power supply units (dv dd , av dd , av dd -p, and ev dd ). we recommend turning off all four of these units at the same time. <2> after power-down, the status of the reset_b pin is undefined. 8. power saving function 8.1 software power saving function (command-driven) the pd9991 includes a power saving function (standby mode) t hat is controlled by command input. for details, see 6.1 standby setting . 8.2 hardware power saving function (by powering down the power supply) in addition to the software power saving function, a hardware power saving function is available. in such cases, note with caution that all data written to registers and memory will be deleted (be sure to rewrite this data after canceling the power saving operation). follow the steps described below when setting hardware power saving. <1> with the reset_b pin set to low level, turn off dv dd , av dd , and av dd -p. <2> continue supplying ev dd since it is used to protect the cpu bus line. <3> be sure to fix the reset_b pin to low level during a hardware power saving operation. follow the steps described below to cancel hardware power saving. <1> with the reset_b pin set to low level, turn on dv dd , av dd , and av dd -p. <2> set the reset_b pin to high level.
pd9991 data sheet s16919ej1v0ds 38 9. setting sequence 9.1 power application steps items target register, etc. 1 cancel hardware reset reset_b pin (low to high) 2 set pll mclk1a, mclk1b, mclk2a, mclk2b 3 set sampling frequency fs 4 cancel pll standby stpll1, stpll2, stref 5 cancel standby stsynth, stdig, stasi, staso, stdac 6 internal clock is valid after canceling standby for stdig and stsynth, normal operation begins after at least 2 ms have elapsed. 9.2 basic sequence for switching among operation modes steps items target register, etc. 1 lower analog volume step by step (recommended) aaulga, aaurga 2 set analog volume mute aaulga, aaurga 3 set standby mode stpll1, stpll2, stref, stsynth, stdig, stasi, staso, stdac 4 switch sound source/audio path slsorce 5 switching surround on/off setting ensrd 6 set sampling frequency fs 7 set asio mode ms, asim, lrclk, slr 8 cancel pll standby stpll1, stpll2, stref 9 cancel standby stsynth, stdig, stasi, staso, stdac 10 internal clock is valid after canceling standby for stdig and stsynth, normal operation begins after at least 2 ms have elapsed. 11 cancel analog volume mute aaulga, aaurga 12 raise analog volume step by step (recommended) aaulga, aaurga remarks 1. during slave mode, input of lrclk and bclk are required. 2. setting of mute after using the analog volume contro l to lower the volume step by step and to raise of the volume after canceling the mute setting are per formed in order to eliminate any audible change in sound that can occur due to single-frame operation e rrors in the digital dat a that is generated while switching. an example of raising and lowering volume step by step is shown below. example step = 1.5 db (minimum unit) cycle (time per step) for raising or lowering = 200 s per step these values are merely an example from our company?s evaluations. adjustments for each set should be made as determined by the manufacturer. 3. the stdig signal is also used to reset operations su ch as digital filter operat ions, so it is required when switching modes.
pd9991 data sheet s16919ej1v0ds 39 9.2.1 mute steps items target register, etc. 1 lower analog volume step by step (recommended) aaulga, aaurga 2 set analog volume mute aaulga, aaurga 9.2.2 standby steps items target register, etc. 1 lower analog volume step by step (recommended) aaulga, aaurga 2 set analog volume mute aaulga, aaurga 3 set standby mode stpll1, stpll2, stref, stsynth, stdig, stasi, staso, stdac 4 cancel pll standby stpll1, stpll2, stref 5 cancel standby stsynth, stdig, stasi, staso, stdac 6 internal clock is valid after canceling standby for stdig and stsynth, normal operation begins after at least 2 ms have elapsed. 7 cancel analog volume mute aaulga, aaurga 8 raise analog volume step by step (recommended) aaulga, aaurga 9.2.3 fs switching steps items target register, etc. 1 lower analog volume step by step (recommended) aaulga, aaurga 2 set analog volume mute aaulga, aaurga 3 set standby mode stpll1, stpll2, stref, stsynth, stdig, stasi, staso, stdac 4 set sampling frequency fs 5 cancel pll standby stpll1, stpll2, stref 6 cancel standby stsynth, stdig, stasi, staso, stdac 7 internal clock is valid after canceling standby for stdig and stsynth, normal operation begins after at least 2 ms have elapsed. 8 cancel analog volume mute aaulga, aaurga 9 raise analog volume step by step (recommended) aaulga, aaurga 9.2.4 path switching steps items target register, etc. 1 lower analog volume step by step (recommended) aaulga, aaurga 2 set analog volume mute aaulga, aaurga 4 switch sound source/audio path slsorce 5 cancel analog volume mute aaulga, aaurga 6 raise analog volume step by step (recommended) aaulga, aaurga caution data may be incorrect in one frame.
pd9991 data sheet s16919ej1v0ds 40 9.2.5 surround switching steps items target register, etc. 1 lower analog volume step by step (recommended) aaulga, aaurga 2 set analog volume mute aaulga, aaurga 3 switching surround on/off setting ensrd 4 cancel analog volume mute aaulga, aaurga 5 raise analog volume step by step (recommended) aaulga, aaurga caution data may be incorrect in one frame. 9.2.6 set asio mode steps items target register, etc. 1 lower analog volume step by step (recommended) aaulga, aaurga 2 set analog volume mute aaulga, aaurga 3 set standby mode stpll1, stpll2, stref, stsynth, stdig, stasi, staso, stdac 4 set asio mode ms, asim, lrclk, slr 5 cancel pll standby stpll1, stpll2, stref 6 cancel standby stsynth, stdig, stasi, staso, stdac 7 internal clock is valid after canceling standby for stdig and stsynth, normal operation begins after at least 2 ms have elapsed. 8 cancel analog volume mute aaulga, aaurga 9 raise analog volume step by step (recommended) aaulga, aaurga caution data may be incorrect in one frame. 9.2.7 ram access steps items target register, etc. 1 after power application reset_b pin (see 9.1 power application .) 2 address specification address specification 3 data transfer data transfer
pd9991 data sheet s16919ej1v0ds 41 9.3 setting sequence example 9.3.1 sound source-dac output (1) power application steps items target register, etc. 1 cancel hardware reset reset_b pin (low to high) 2 set pll mclk1a, mclk1b, mclk2a, mclk2b 3 set sampling frequency fs 32 khz 4 sound source/audio path switching slsorce = 0 5 cancel pll standby stpll1 = stpll2 = stref = 1 6 cancel standby stdig = stsynth = stdac = 1 7 internal clock is valid after canceling standby for stdig and stsynth, normal operation begins after at least 2 ms have elapsed. (2) sound source setting (3) sound source data transfer (4) volume up steps items target register, etc. 8 cancel analog volume mute aaulga, aaurga 9 raise analog volume step by step (recommended) aaulga, aaurga 9.3.2 sound source-aso output (1) power application steps items target register, etc. 1 cancel hardware reset reset_b pin (low to high) 2 set pll mclk1a, mclk1b, mclk2a, mclk2b 3 set sampling frequency fs 32 khz 4 sound source/audio path switching slsorce = 0 5 set asio mode ms, asim, lrclk, slr 6 cancel pll standby stpll1 = stpll2 = stref = 1 7 cancel standby stdig = stsynth = stdac = 1 8 internal clock is valid after canceling standby for stdig and stsynth, normal operation begins after at least 2 ms have elapsed. (2) sound source setting (3) sound source data transfer
pd9991 data sheet s16919ej1v0ds 42 9.3.3 asi-dac output (1) power application steps items target register, etc. 1 cancel hardware reset reset_b pin (low to high) 2 set pll mclk1a, mclk1b, mclk2a, mclk2b 3 set sampling frequency fs 32 khz, 44.1 khz, or 48 khz 4 sound source/audio path switching slsorce = 1 5 set asio mode ms, asim, lrclk, slr 6 cancel pll standby stpll1 = stref = 1 7 cancel standby stdig = stdac = 1 8 internal clock is valid after canceling standby for stdig, normal operation begins after at least 2 ms have elapsed. (2) music data transmission (3) volume up steps items target register, etc. 9 cancel analog volume mute aaulga, aaurga 10 raise analog volume step by step (recommended) aaulga, aaurga 9.3.4 asi-aso output (1) power application steps items target register, etc. 1 cancel hardware reset reset_b pin (low to high) 2 set pll mclk1a, mclk1b, mclk2a, mclk2b 3 set sampling frequency fs 32 khz, 44.1 khz, or 48 khz 4 sound source/audio path switching slsorce = 1 5 set asio mode ms, asim, lrclk, slr 6 cancel pll standby stpll1 = stref = 1 7 cancel standby stdig = stdac = 1 8 internal clock is valid after canceling standby for stdig, normal operation begins after at least 2 ms have elapsed. (2) music data transmission
pd9991 data sheet s16919ej1v0ds 43 9.4 relation between setting modes and internal oper ations (relation with synchronization clock) table 9-1. relation between setting modes and intern al operations (relation with synchronization clock) register pin (signal) status function ms slsorce stasi staso lrclk, bclk sync. clock sync_lr asi aso line_out (dac) actual use remark slave mode, sound source path, standby during asi and aso 0 slave 0 synth 0 off 0 off input/ internal low internal invalid hi-z out sound source- dac even though slave mode has been set, the internal clock operates. slave mode, sound source path, asi standby, aso output 0 slave 0 synth 0 off 1 on signal input external invalid out out sound source- aso uses external synchronization clock. if the external lrclk signal has not yet been input, outputs are stopped. slave mode, audio path, asi input, aso standby 0 slave 1 audio 1 on 0 off signal input external in hi-z out asi-dac uses external synchronization clock. if the external lrclk signal has not yet been input, outputs are stopped. slave mode, audio path, asi input, aso output 0 slave 1 audio 1 on 1 on signal input external in out out asi-aso uses external synchronization clock. if the external lrclk signal has not yet been input, outputs are stopped. master mode, sound source path, standby during asi and aso 1 master 0 synth 0 off 0 off low output internal invalid hi-z out sound source- dac the internal clock operates. master mode, sound source path, asi standby, aso output 1 master 0 synth 0 off 1 on signal output internal invalid out out sound source- aso the internal clock operates. master mode, audio path, asi input, aso standby 1 master 1 audio 1 on 0 off signal output internal in hi-z out asi-dac the internal clock operates. master mode, audio path, asi input, aso output 1 master 1 audio 1 on 1 on signal output internal in out out asi-aso the internal clock operates. remark the operations in table 9-1 apply to the operations in mixing mode ( address 05h, mix = 1). therefore, when setting mixing (mix = 1) while the asio is in slav e mode (address 08h, ms = 1), be sure to set stasi = 1 and input bclk and lrclk. when stopping the asi input and using the sound source only, retain the settings of ms = 1, mix = 1, and stasi = 1 or set mix = 0 and slsorce = 0.
pd9991 data sheet s16919ej1v0ds 44 10. standby mode standby mode for various blocks 10.1 clock supply during the standby mode for pll1 and pll2, access is enabl ed only for the standby regi ster at address 00h, the master clock setting registers at addresses 01h, 02h , 03h, and 04h, and the general-purpose output pin setting register at address 0eh. to use dvx, dac and asio, the p ll1 standby mode must be canceled. to use the sound source logic block, the pll2 standby mode must be canceled. the supply of clock signals from the pll to various blocks is illustrated in figure 10-1. figure 10-1. destination of cloc ks supplied from pll1 and pll2 pll1 clkin cpu i/f sound source logic block dvx dac pll1 pll1 pll2 vref/iref asio asi aso pll2 pd9991 pll1
pd9991 data sheet s16919ej1v0ds 45 11. reference schematics 11.1 line out pins (lineout_l and lineout_r) figure 11-1. example of connection to line out pin + + pd9991 dac lineout_l lineout_r 47 k ? 47 k ? 4.7 f 4.7 f stereo output 11.2 reference power supply voltage and current supply pins (vref and iref) figure 11-2. handling of vref and iref pins band gap reference iref vref 56 k ? 0.22 f pd9991 the vref and iref blocks include the following functions. ? reference voltage is generated using band gap ? the reference current is generated usi ng this reference voltage and an external resistance, and is supplied to all analog circuits. the vref and iref blocks operates when stref = 1 in the stnby register. normal mode is set within 1.0 ms after this stref bit is set (= 1). cautions 1. be sure to connect a 56 k ? resistor between the iref pin and agnd. do not connect any other resistors to the iref pin. 2. be sure to connect a 0.22 f ( 20%) capacitor between the vref pin and agnd. do not connect any other capacitors to the vref pin.
pd9991 data sheet s16919ej1v0ds 46 11.3 power supply whenever possible, avoid placing a decoupling capacitor close to any of the pd9991?s pins. figure 11-3. placement of decoupling capacitor pd9991 av dd av dd agnd av dd- p agnd-p 0.1 f 0.1 f agnd dv dd ev dd egnd ev dd dgnd dv dd 0.1 f 0.1 f egnd dgnd the pairing of pins between the power supply (with decoupling capacitor) and gnd is as follows (pin numbers are indicated in parentheses). av dd (1e) ? agnd (1d) av dd -p (2g) ? agnd-p (1h) dv dd (9k) ? dgnd (5k) dv dd (10d) ? dgnd (10j) ev dd (9c) ? egnd (6a) dv dd (9a) ? egnd (6a) caution ev dd is used for digital operations. therefore, it is recommended to use a different power supply to the analog power supplies (av dd and av dd -p) to avoid affecting the analog characteristics.
pd9991 data sheet s16919ej1v0ds 47 11.4 pin outline schematics input pin output pin pin outline schematic tm0 to tm4, po0 to po3, a1, a0, cs_b, wr_b, rd_b, d0 to d7, reset_b, lrclk, bclk, asi, ps, trsck, clk8k, rdata tm3, tm4, po0 to po3, a0, d0 to d7, int_b, vib, led, lrclk, bclk, aso ev dd egnd input pin output pin iref, vref iref, vref, lineout_l, lineout_r av dd agnd input pin output pin clkin ? av dd -p agnd-p input pin output pin
pd9991 data sheet s16919ej1v0ds 48 12. electrical specifications 12.1 absolute maximum ratings parameter symbol conditions rating unit dv dd for digital ports ?0.3 to +2.0 v ev dd for i/o pins ?0.3 to +4.0 v av dd for analog ports ?0.3 to +4.0 v supply voltage av dd -p for pll ?0.3 to +4.0 v input voltage v i ?0.3 to +4.0 v output voltage v o v i /v o < ev dd + 0.5 v ?0.3 to +4.0 v power dissipation p d 300 mw storage temperature t stg ?50 to +125 c caution product quality may suffer if the absolute m aximum rating is exceeded e ven momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefor e the product must be used under conditions that ensure that the absolute maxi mum ratings are not exceeded. 12.2 recommended operating conditions parameter symbol conditions min. typ. max. unit dv dd 1.425 1.5 1.575 v ev dd 1.71 3.0 3.3 v av dd 2.85 3.0 3.15 v operating voltage av dd -p 2.85 3.0 3.15 v input voltage v i ? 20 to +85 c 0 ev dd v operating ambient temperature t a ?20 +85 c 12.3 capacitance (t a = + 25 c, dv dd = 0 v, ev dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 10 pf output capacitance c o 10 pf i/o capacitance c io f = 1 mhz, pins other than those tested: 0 v 10 pf
pd9991 data sheet s16919ej1v0ds 49 12.4 dc characteristics (t a = ? 20 to +85 c, with dv dd and ev dd within recommended operating condition range) parameter symbol conditions min. typ. max. unit input voltage, high v ihn 0.8 ev dd ev dd v input voltage, low v iln 0 0.2 ev dd v v oh3 evdd = 3.0 v, i oh = ?1 ma (led, vib = ?4 ma) 0.8 ev dd v output voltage, high v oh18 evdd = 1.8 v, i oh = ?1 ma (led, vib = ?1.5 ma) 0.8 ev dd v v ol3 evdd = 3.0 v, i ol = +1 ma (led, vib = +4 ma) 0.2 ev dd v output voltage, low v ol18 evdd = 1.8 v, i ol = +1 ma (led, vib = +1.5 ma) 0.2 ev dd v input leakage current, high i lhn v i = ev dd 0 10 a input leakage current, low i lln v i = 0 v ?10 0 a high-impedance leakage current i zi 0 v v i ev dd 0 ?10 a common ratings for switching characteristics 0.8 ev dd 0.5 ev dd 0.2 ev dd 0.8 ev dd 0.5 ev dd 0.2 ev dd test points 0.5 ev dd 0.5 ev dd test points output input
pd9991 data sheet s16919ej1v0ds 50 12.5 ac characteristics (unless otherwise specified, t a = ? 20 to + 85 c, with v dd and ev dd within recommended operating condition range) 12.5.1 clock timing requirements parameter symbol conditions min. typ. max. unit clkin input frequency f clkin v clkin = 0.5v p-p 2.688 16.128 mhz clkin input level v clkin f clkin = 2.688 mhz to 16.128 mhz note 1 0.5 note 2 v p-p pll lockup time t lpll 1.0 ms notes 1. clkin input to be used as pll input s hould have capacitive coupling (1000 pf). 2. the maximum input level for clkin should not exceed the power supply (av dd -p) potential. 12.5.2 reset timing requirements (ev dd = 3.0 v) parameter symbol conditions min. typ. max. unit reset_b low-level width t w(rl) 200 ns reset_b recovery time t rec(r) 200 ns timing requirements (ev dd = 1.8 v) parameter symbol conditions min. typ. max. unit reset_b low-level width t w(rl) 225 ns reset_b recovery time t rec(r) 225 ns reset timing reset_b t w(rl) t rec(r)
pd9991 data sheet s16919ej1v0ds 51 12.5.3 host interface timing requirements (ev dd = 3.0 v) parameter symbol conditions min. typ. max. unit rd_b width t wrd 100 ns wr_b width t wwr 100 ns rd_b recovery time t rcrd during read access to sound source register 30 ns rd_b recovery time t rcrd during read access to other than sound source register 200 ns wr_b recovery time t rcwr during write access to sound source register 60 ns wr_b recovery time t rcwr during consecutive access to write data to and read data from sound source register 100 ns wr_b recovery time t rcwr during write access to other than sound source register 200 ns data setup time t sudi wr_b 50 ns data hold time t hdi wr_b 0 ns a, cs_b setup time t suaw wr_b 15 ns a, cs_b hold time t haw wr_b 0 ns a, cs_b setup time t suar rd_b 0 ns a, cs_b hold time t har rd_b 0 ns timing requirements (ev dd = 1.8 v) parameter symbol conditions min. typ. max. unit rd_b width t wrd 125 ns wr_b width t wwr 125 ns rd_b recovery time t rcrd during read access to sound source register 55 ns rd_b recovery time t rcrd during read access to other than sound source register 225 ns wr_b recovery time t rcwr during write access to sound source register 85 ns wr_b recovery time t rcwr during consecutive access to write data to and read data from sound source register 125 ns wr_b recovery time t rcwr during write access to other than sound source register 225 ns data setup time t sudi wr_b 80 ns data hold time t hdi wr_b 0 ns a, cs_b setup time t suaw wr_b 75 ns a, cs_b hold time t haw wr_b 0 ns a, cs_b setup time t suar rd_b 0 ns a, cs_b hold time t har rd_b 0 ns switching characteristics (ev dd = 3.0 v) parameter symbol conditions min. typ. max. unit data access time t accdo rd_b , i sink = 1 ma 100 ns data hold time t ddo rd_b , i sink = 1 ma 0 30 ns
pd9991 data sheet s16919ej1v0ds 52 switching characteristics (ev dd = 1.8 v) parameter symbol conditions min. typ. max. unit data access time t accdo rd_b , i sink = 1 ma 125 ns data hold time t ddo rd_b , i sink = 1 ma 0 60 ns host interface read timing cs_b a0, a1 wr_b rd_b d7 to d0 address write cycle data read cycle read address read data d.c d.c d.c next address t har t suar t wrd t rcrd t ddo t accdo host interface write timing cs_b a0, a1 wr_b rd_b d7 to d0 address write cycle data write cycle t suaw t haw t wwr t rcwr t sud1 t hd1 write address write data d.c d.c h d.c next dddress
pd9991 data sheet s16919ej1v0ds 53 12.5.4 audio serial interface timing requirements (ev dd = 3.0 v) parameter symbol conditions min. typ. max. unit lrclk cycle time t clr 1/fs ns bclk cycle time t cbc when set to 64 bits per frame note 1/(fs 64) ns bclk high-/low-level width t wbc t cbc /2 ns bclk rise/fall time t rfbc 20 ns lrclk rising edge delay time t drlrc bclk 50 ns lrclk falling edge delay time t dflrc bclk 50 ns asi input setup time t suaser bclk 25 ns asi input hold time t haser bclk 25 ns note the configuration of each frame varies according to t he settings in the bfs[4:0] bi ts of the slfs register (07h). timing requirements (ev dd = 1.8 v) parameter symbol conditions min. typ. max. unit lrclk cycle time t clr 1/fs ns bclk cycle time t cbc when set to 64 bits per frame note 1/(fs 64) ns bclk high-/low-level width t wbc t cbc /2 ns bclk rise/fall time t rfbc 20 ns lrclk rising edge delay time t drlrc bclk 50 ns lrclk falling edge delay time t dflrc bclk 50 ns asi input setup time t suaser bclk 50 ns asi input hold time t haser bclk 50 ns note the configuration of each frame varies according to t he settings in the bfs[4:0] bi ts of the slfs register (07h). switching characteristics ( ev dd = 3.0 v) parameter symbol conditions min. typ. max. unit lrclk output delay time t dlrc bclk 50 ns aso output delay time t daser bclk ?12.5 +25 ns switching characteristics ( ev dd = 1.8 v) parameter symbol conditions min. typ. max. unit lrclk output delay time t dlrc bclk 50 ns aso output delay time t daser bclk ?37.5 +50 ns
pd9991 data sheet s16919ej1v0ds 54 audio serial i/o timing (slave mode) bclk t rfbc asi aso t wbc t wbc t cbc t daser t rfbc t drlrc t dflrc lrclk t suaser t haser (input) (input) (output) (input) audio serial i/o timing (master mode) bclk t rfbc asi aso t wbc t wbc t cbc t daser t rfbc t dlrc t dlrc lrclk t suaser t haser (output) (output) (output) (input)
pd9991 data sheet s16919ej1v0ds 55 12.6 analog characteristics the propagation characteristics fr om the d/a converter to the line output are described below. unless otherwise specified, the following conditions must be met. d/a converter input level input = 0 dbfs (d/a converter?s full scale input is defined as 0 dbfs) d/a converter input frequency f in = 997 hz sampling frequency fs = 48 khz ambient temperature t a = 25c power supply voltage av dd = 3.0 v output load r l = 10 k ? parameter symbol conditions min. typ. max. unit maximum output level v o volume = 0 db 1.8 2.0 ? v p-p gain error 1 ge max volume = 0 db, 0 dbr = 2.0 v p-p ?1 0 +1 dbr gain error 2 ge min volume = ? 45 db, value relative to g emax reference ? 47 ?45 ?43 db gain adjustment resolution g step volume = when 0 to ? 45 db, differential error 1 1.5 2 db thd thd volume = 0 db, f = 20 khz to 19.2 khz ? ?80 ?74 db frequency characteristics 100 hz to 19.2 khz gf volume = 0 db, input = ?10 dbm@997 hz, output when at 997 hz is us ed as 0 db reference ?1 0 +1 db dynamic range snd volume = 0 db, input = ?60 dbfs, f = 20 khz to 19.2 khz, a-wgt filter 80 86 ? db
pd9991 data sheet s16919ej1v0ds 56 12.7 mode-specific current consumption characteristics unless otherwise specified, the following conditions must be met. sound source master clock = 55.104 mhz master clock other than sound s ource master clock = 24.576 mhz d/a converter input level input = 0 dbfs (d/a co nverter?s full scale input is defined as 0 dbfs) d/a converter input frequency f in = 1020 hz sampling frequency fs = 48 khz ambient temperature t a = 25 c power supply voltage av dd = av dd -p = ev dd = 3.0 v, dv dd = 1.5 v output load r l = 10 k ? parameter symbol conditions power supply pin min. typ. max. unit dv dd ? 30 45 ma av dd ? 8 14 ma av dd -p ? 3 6 ma current during output from sound source to dac i dd1 av dd + av dd -p + dv dd current when stdig = stpll2 = stpll1 = stsynth = stdac = stref = 1, slsorce = 0 and sound generator is operating normally ev dd note ? ? 1 ma dv dd ? 30 45 ma av dd ? 4 6 ma av dd -p ? 3 6 ma current during output from sound source to aso idd2 avdd + avdd-p + dvdd current when stdig = stpll2 = stpll1 = stsynth = stref = 1, slsorce = 0, aso = 1 and sound generator is operating normally ev dd note ? ? 5 ma dv dd ? 5 8 ma av dd ? 8 14 ma av dd -p ? 2 4 ma current during output from asi to dac i dd3 av dd + av dd -p + dv dd current when stdig = stpll1 = stdac = stref = 1, slsorce = 1, asi = 1 ev dd note ? ? 1 ma dv dd ? 5 8 ma av dd ? 4 6 ma av dd -p ? 2 4 ma current during output from asi to aso i dd4 av dd + av dd -p + dv dd current when stdig = stpll1 = stref = 1, slsorce = 1, asi = aso = 1 ev dd note ? ? 5 ma dv dd ? 5 300 a av dd ? 1 5 a av dd -p ? 1 5 a standby current (command-driven) i stb av dd + av dd -p + dv dd current when stdig = stpll2 = stpll1 = stasi = staso = stsynth = stdac = stref = 0 ev dd note ? ? 1 ma note the ev dd pin current is measur ed when there is no load. in the actual operation of the pd9991, the ev dd pin current differs depending on the external environment such as the clock rate, load capacitance, and load resistance.
pd9991 data sheet s16919ej1v0ds 57 13. package drawing item dimensions d e v w e a a1 a2 b x y y1 zd ze 6.00 0.10 6.00 0.10 0.18 0.05 0.15 0.50 0.65 0.20 0.83 0.10 (unit:mm) 0.32 0.05 0.05 0.08 0.20 0.75 0.75 p65f9-50-ba1 a a1 a2 1 a b c d e f g h j k 2 3 4 5 6 7 8 9 10 zd ze index mark d e s e y1 s s y s v s x bab m ? s wb s wa b a 65-pin tape fbga (6x6)
pd9991 data sheet s16919ej1v0ds 58 14. recommended soldering conditions the pd9991 should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http ://www.necel.com/pkg/en/mount/index.html) ? pd9991f9-ba1: 65-pin tape fbga (6 6) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature : 250 c, time : 80 sec. max. (at 220 c or higher), count : two times or less, exposure limit : 7 days note (after that prebaking is necessary at 125 c for 10 to 72 hours) ir50-107-2 note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period.
pd9991 data sheet s16919ej1v0ds 59 [memo]
pd9991 data sheet s16919ej1v0ds 60 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd9991 data sheet s16919ej1v0ds 61 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j03.4 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 succursale fran?aise filiale italiana milano, italy tel: 02-66 75 41 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 tyskland filial taeby, sweden tel: 08-63 80 820 united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
pd9991 the information in this document is current as of january, 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1

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